ME>Потеряете. Без ассемблера не обойтись.
ME>На x86 атомарность чтения байта, слова, двойнога слова гарантируется только на однопроцессорной машине. На многопроцессорной придется использовать префикс lock, чего без asm'a не сделать.
ME>P.S. В этом случае volatile не нужен.
Выдержка из IA-32 Intel® Architecture Software Developer’s Manual
7.1.1. Guaranteed Atomic Operations
The Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors guarantee that the
following basic memory operations will always be carried out atomically:
• Reading or writing a byte.
• Reading or writing a word aligned on a 16-bit boundary.
• Reading or writing a doubleword aligned on a 32-bit boundary.
The Pentium 4, Intel Xeon, and P6 family, and Pentium processors guarantee that the following
additional memory operations will always be carried out atomically:
• Reading or writing a quadword aligned on a 64-bit boundary.
• 16-bit accesses to uncached memory locations that fit within a 32-bit data bus.
The P6 family processors guarantee that the following additional memory operation will always
be carried out atomically:
• Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a 32-byte cache
line.
Accesses to cacheable memory that are split across bus widths, cache lines, and page boundaries
are not guaranteed to be atomic by the Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486
processors. The Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that
permit external memory subsystems to make split accesses atomic; however, nonaligned data
accesses will seriously impact the performance of the processor and should be avoided.
